EDN

Get a hands-on tutorial in FPGA design at ESC Silicon Valley

I just heard from my chum Jason Pecor at Alorium Technology. Jason and his colleague, Bryan Craker, will be giving a 2-hour tutorial at ESC Silicon Valley 2016. Titled A Novel Hands-On Approach to ...
Semiconductor Engineering

Scaling Open-Source HW Accelerator for Deep NN Inference (UDE, Fraunhofer IMS)

Researchers from University of Duisburg-Essen and Fraunhofer Institute for Microelectronic Circuits and Systems have ...
EDN

A tutorial on tools, techniques, and methodology to improve FPGA designer productivity

What is the biggest factor affecting the productivity of FPGA design cycles? Many designers say achieving timing closure is critical in getting a design to market – and with good reason. Achieving ...
Design-Reuse

Avery Design Systems Announces SimAccel FPGA Accelerator

TEWKSBURY, MA., --August 5, 2019 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of the SimAccel FPGA-based accelerator to ...
New Electronics

AMD unveils FPGA-based accelerator for ultra efficient electronic trading

AMD has unveiled its new Alveo UL3524 accelerator card, a fintech accelerator that’s been designed for ultra-low latency electronic trading applications. Already deployed by a number of trading firms, ...
Design-Reuse

CAST Introduces GZIP Accelerator Through New Intel FPGA Data Center Acceleration Ecosystem

WOODCLIFF LAKE, NJ USA, Oct. 17, 2017 – A hardware accelerator that addresses the data compression and storage optimization needs of performance-critical data center applications is now available from ...
Embedded

Moving from FPGA to ASIC for your AI chip? Here’s what you should know

Perhaps you are designing an embedded inference engine for edge computing. Or you are taking the next step in automotive vision processing. Or maybe you have an insight that can challenge Nvidia and ...