RISC-V北美峰会上展示了采用新型矢量处理器、高速接口和外围子系统的最新CPU核心，并同步推出了配套的参考板、软件设计套件(SDK)和工具链。此次峰会还提前呈现了日益成熟的RISC-V设计生态系统。 RISC-V北美峰会在加利福尼亚州圣克拉拉举行，其间展示了采用 ...

With its blend of open-source freedoms with the benefits of standardization, the RISC-V (risk-five) Foundation is attracting widespread industry interest. Its core specifications are stable and on the ...

3月24日，由阿里巴巴达摩院主办的2026玄铁RISC-V生态大会在上海举行。高通、Arteris、Canonical、SHD Group、海尔、中兴通讯、全志科技、北京智芯微、南芯科技等全球数百家产学研机构齐聚一堂，分享RISC-V前沿实践。会上，阿里巴巴达摩院发布高性能RISC-V CPU玄铁 ...

Learn how to incorporate Questa VIP into your existing RISC-V verification flow. This step-by-step tutorial, prepared by Codasip’s verification experts, explains the concepts of combining ...

RISC-V, pronounced “risk five,” is a modern open-source instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. In simple terms, it’s like a blueprint that ...

What if the future of computing wasn’t locked behind proprietary architectures? Imagine a world where developers and hobbyists alike could harness the power of open source hardware to build, innovate, ...