// this is exactly attainable at the PLL from a 12 MHz crystal: FBDIV = // 133 (so VCO of 1596 MHz), PD1 = 6, PD2 = 2. This function will set the // system PLL to 133 MHz and set the clk_sys divisor ...
#define NRFX_ATOMIC_OP(asm_op, old_val, new_val, ptr, value) \ old_val = nrfx_atomic_internal_##asm_op(ptr, value, &new_val) * @brief Atomic operation generic macro ...
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